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6818 A6818xA LOAD SUPPLY SERIAL DATA OUT OUT 32 OUT 31 OUT 30 OUT 29 OUT 28 OUT 27 OUT 26 OUT 25 OUT 24 OUT 23 OUT 22 OUT 21 OUT 20 OUT 19 OUT 18 OUT 17 BLANKING GROUND 1 2 3 4 5 6 7 8 9 REGISTER REGISTER LATCHES LATCHES DABiC-IV, 32-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER LOGIC SUPPLY SERIAL DATA IN OUT 1 OUT 2 OUT 3 OUT 4 OUT 5 OUT 6 OUT 7 OUT 8 OUT 9 OUT 10 OUT 11 OUT 12 OUT 13 OUT 14 OUT 15 OUT 16 STROBE CLOCK VBB VDD 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 The A6818- devices combine a 32-bit CMOS shift register, accompanying data latches and control circuitry with bipolar sourcing outputs and pnp active pull downs. Designed primarily to drive vacuum-fluorescent displays, the 60 V and -40 mA output ratings also allow these devices to be used in many other peripheral power driver applications. The A6818- features an increased data input rate (compared with the older UCN/UCQ5818-F) and a controlled output slew rate. The CMOS shift register and latches allow direct interfacing with microprocessor-based systems. With a 3.3 V or 5 V logic supply, typical serial-data input rates are up to 33 MHz. A CMOS serial data output permits cascade connections in applications requiring additional drive lines. Similar devices are available as the A6809- and A6810- (10 bits), A6811- (12 bits), and A6812- (20 bits). The A6818- output source drivers are npn Darlingtons, capable of sourcing up to 40 mA. The controlled output slew rate reduces electromagnetic noise, which is an important consideration in systems that include telecommunications and/or microprocessors and to meet government emissions regulations. For inter-digit blanking, all output drivers can be disabled and all sink drivers turned on with a BLANKING input high. The pnp active pull-downs will sink at least 2.5 mA. Two temperature ranges are available for optimum performance in commercial (suffix S-) or industrial (suffix E-) applications. Package styles are provided for through-hole DIP (suffix -A) or minimum-area surface-mount PLCC (suffix -EP). Copper lead frames, low logicpower dissipation, and low output-saturation voltages allow these devices to drive most multiplexed vacuum-fluorescent displays over the maximum operating temperature range. Data Sheet 26182.128A 10 11 12 13 14 15 16 17 18 19 20 BLNK ST CLK 22 21 Dwg. PP-029-4 ABSOLUTE MAXIMUM RATINGS at TA = 25C Logic Supply Voltage, VDD ................... 7.0 V Driver Supply Voltage, VBB ................... 60 V Continuous Output Current Range, IOUT ......................... -40 mA to +15 mA Input Voltage Range, VIN ....................... -0.3 V to VDD + 0.3 V Package Power Dissipation, PD ........................................ See Graph Operating Temperature Range, TA (Suffix `E-') .................. -40C to +85C (Suffix `S-') .................. -20C to +85C Storage Temperature Range, TS ............................... -55C to +125C FEATURES I Controlled Output Slew Rate I Low Output-Saturation Voltages I High-Speed Data Storage I Low-Power CMOS Logic I 60 V Minimum and Latches Output Breakdown I Improved Replacements I High Data Input Rate for SN75518N, SN75518NF, I PNP Active Pull-Downs UCN5818-, and UCQ5818- Complete part number includes a suffix to identify operating temperature range (E- or S-) and package type (-A or -EP). Always order by complete part number, e.g., A6818SEP . Caution: These CMOS devices have input static protection (Class 2) but are still susceptible to damage if exposed to extremely high static electrical charges. 6818 32-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER TYPICAL INPUT CIRCUIT OUT30 OUT31 A6818xEP SERIAL DATA OUT LOAD SUPPLY LOGIC SUPPLY SERIAL DATA IN OUT32 OUT 1 OUT2 41 NC OUT3 40 VDD 44 43 V DD VBB 42 6 3 5 4 2 1 OUT29 7 8 9 10 2 39 38 37 36 OUT 4 IN REGISTER REGISTER LATCHES LATCHES 11 12 Dwg. EP-010-5 35 34 33 19 32 31 30 29 OUT13 NC 13 14 15 16 OUT19 17 OUT 8 BLNK CLK 20 ST 27 OUT14 18 23 19 24 25 21 22 OUT17 BLANKING GROUND STROBE OUT15 NC OUT18 OUT 16 26 CLOCK NC 28 Dwg. PP-059-2 TYPICAL OUTPUT DRIVER V BB 3.0 ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS 2.5 SUFFIX 'A', R JA = 36C/W OUTN 2.0 Dwg. EP-021-19 1.5 SUFFIX 'EP', RJA = 46C/W 1.0 0.5 0 25 50 75 100 125 AMBIENT TEMPERATURE IN C 150 Dwg. GP-025A 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright (c) 1998, 2000 Allegro MicroSystems, Inc. 6818 32-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER FUNCTIONAL BLOCK DIAGRAM CLOCK SERIAL DATA IN STROBE V DD LOGIC SUPPLY SERIAL DATA OUT SERIAL-PARALLEL SHIFT REGISTER LATCHES BLANKING MOS BIPOLAR LOAD SUPPLY VBB GROUND OUT 1 OUT 2 OUT 3 OUT N Dwg. FP-013-1 TRUTH TABLE Serial Shift Register Contents Data Clock Input Input I1 I2 I3 ... IN-1 IN H L X H L R1 R2 ... R1 R2 ... RN-2 RN-1 RN-2 RN-1 RN-1 RN X X Serial Data Strobe Output Input RN-1 RN-1 RN X PN L H R1 R2 R3 ... P1 P2 P3 ... X L = Low Logic Level H = High Logic Level X = Irrelevant Latch Contents I1 I2 I3 ... IN-1 IN Blanklng Output Contents I1 I2 I3 ... IN-1 IN R1 R2 R3 ... X X X ... RN-1 RN PN-1 PN X X L H P1 P2 P3 ... PN-1 PN L L L ... L L P1 P2 P3 ... PN-1 PN X X ... P = Present State R = Previous State www.allegromicro.com 6818 32-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER ELECTRICAL CHARACTERISTICS at TA = +25C (A6818S-) or over operating temperature range (A6818E- and A6818K-), VBB = 60 V unless otherwise noted. Limits @ VDD = 3.3 V Characteristic Output Leakage Current Output Voltage Symbol ICEX VOUT(1) VOUT(0) Output Pull-Down Current Input Voltage IOUT(0) VIN(1) VIN(0) Input Current IIN(1) IIN(0) Input Clamp Voltage Serial Data Output Voltage VIK VOUT(1) VOUT(0) Maximum Clock Frequency Logic Supply Current fc IDD(1) IDD(0) Load Supply Current IBB(1) IBB(0) Blanking-to-Output Delay tdis(BQ) ten(BQ) Strobe-to-Output Delay tp(STH-QL) tp(STH-QH) Output Fall Time Output Rise Time Output Slew Rate tf tr dV/dt All Outputs High All Outputs Low All Outputs High, No Load All Outputs Low CL = 30 pF, 50% to 50% CL = 30 pF, 50% to 50% RL = 2.3 k, CL 30 pF RL = 2.3 k, CL 30 pF RL = 2.3 k, CL 30 pF RL = 2.3 k, CL 30 pF RL = 2.3 k, CL 30 pF IOUT = 200 A VIN = VDD VIN = 0.8 V IIN = -200 A IOUT = -200 A IOUT = 200 A Test Conditions VOUT = 0 V IOUT = -25 mA IOUT = 1 mA VOUT = 5 V to VBB Mln. -- 57.5 -- 2.5 2.2 -- -- -- -- 2.8 -- 10 -- -- -- -- -- -- -- -- 2.4 2.4 4.0 -- Typ. <-0.1 58.3 1.0 5.0 -- -- <0.01 <-0.01 -0.8 3.05 0.15 33 0.25 0.25 4.5 0.2 0.7 1.8 0.7 1.8 -- -- -- 50 Max. -15 -- 1.5 -- -- 1.1 1.0 -1.0 -1.5 -- 0.3 -- 0.75 0.75 9.0 20 2.0 3.0 2.0 3.0 12 12 20 -- Limits @ VDD = 5 V Min. -- 57.5 -- 2.5 3.3 -- -- -- -- 4.5 -- 10 -- -- -- -- -- -- -- -- 2.4 2.4 4.0 -- Typ. <-0.1 58.3 1.0 5.0 -- -- <0.01 <-0.01 -0.8 4.75 0.15 33 0.3 0.3 4.5 0.2 0.7 1.8 0.7 1.8 -- -- -- 50 Max. -15 -- 1.5 -- -- 1.7 1.0 -1.0 -1.5 -- 0.3 -- 1.0 1.0 9.0 20 2.0 3.0 2.0 3.0 12 12 20 -- Units A V V mA V V A A V V V MHz mA mA mA A s s s s s s V/s ns Clock-to-Serial Data Out Delay tp(CH-SQX) Negative current is defined as coming out of (sourcing) the specified device terminal. Typical data is is for design information only and is at TA = +25C. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 6818 32-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER TIMING REQUIREMENTS and SPECIFICATIONS (Logic Levels are VDD and Ground) C CLOCK A SERIAL DATA IN DATA 50% B 50% t p(CH-SQX) SERIAL DATA OUT D STROBE 50% 50% DATA E BLANKING LOW = ALL OUTPUTS ENABLED t p(STH-QH) t p(STH-QL) 90% OUT N DATA 10% Dwg. WP-029 HIGH = ALL OUTPUTS BLANKED (DISABLED) BLANKING 50% t dis(BQ) t en(BQ) OUT N tr 90% 10% tf DATA A. Data Active Time Before Clock Pulse (Data Set-Up Time), tsu(D) ......................................... 25 ns B. Data Active Time After Clock Pulse (Data Hold Time), th(D) ............................................... 25 ns C. Clock Pulse Width, tw(CH) ............................................... 50 ns D. Time Between Clock Activation and Strobe, tsu(C) ....... 100 ns E. Strobe Pulse Width, tw(STH) ............................................. 50 ns NOTE - Timing is representative of a 10 MHz clock. Significantly higher speeds are attainable. Dwg. WP-030 Information present at any register is transferred to the respective latch when the STROBE is high (serial-to-parallel conversion). The latches will continue to accept new data as long as the STROBE is held high. Applications where the latches are bypassed (STROBE tied high) will require that the BLANKING input be high during serial data entry. When the BLANKING input is high, the output source drivers are disabled (OFF); the pnp active pull-down sink drivers are ON. The information stored in the latches is not affected by the BLANKING input. With the BLANKING input low, the outputs are controlled by the state of their respective latches. Serial Data present at the input is transferred to the shift register on the logic "0" to logic "1" transition of the CLOCK input pulse. On succeeding CLOCK pulses, the registers shift data information towards the SERIAL DATA OUTPUT. The SERIAL DATA must appear at the input prior to the rising edge of the CLOCK input waveform. www.allegromicro.com 6818 32-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER A6818EA & A6811SA Dimensions in Inches (controlling dimensions) 40 0.015 0.008 21 0.700 MAX 0.580 0.485 0.600 BSC 1 2 0.070 0.030 3 4 2.095 1.980 20 0.100 BSC 0.005 MIN 0.250 MAX 0.015 MIN 0.200 0.115 0.022 0.014 Dwg. MA-003-40 in Dimensions in Millimeters (for reference only) 40 0.381 0.204 21 17.78 14.73 12.32 MAX 15.24 BSC 1 2 1.77 0.77 3 4 53.2 50.3 2.54 BSC 20 0.13 MIN 6.35 MAX 0.39 MIN 5.08 2.93 0.558 0.356 Dwg. MA-003-40 mm NOTES: 1. Exact body and lead configuration at vendor's option within limits shown. 2. Lead spacing tolerance is non-cumulative. 3. Lead thickness is measured at seating plane or below. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 6818 32-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER A6818EEP & A6818SEP Dimensions in Inches (controlling dimensions) 28 18 29 0.319 0.291 0.021 0.013 0.695 0.685 0.656 0.650 0.319 0.291 0.050 BSC INDEX AREA 17 0.032 0.026 39 7 40 0.020 MIN 44 1 2 6 0.656 0.650 0.695 0.685 Dwg. MA-005-44A in 0.180 0.165 Dimensions in Millimeters (for reference only) 28 18 29 8.10 7.39 0.533 0.331 17.65 17.40 16.662 16.510 INDEX AREA 17 0.812 0.661 8.10 7.39 1.27 BSC 39 7 40 0.51 MIN 44 16.662 16.510 1 2 6 4.57 4.20 17.65 17.40 Dwg. MA-005-44A mm NOTES: 1. Exact body and lead configuration at vendor's option within limits shown. 2. Lead spacing tolerance is non-cumulative. www.allegromicro.com 6818 32-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 |
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